library verilog;
use verilog.vl_types.all;
entity dti_asym_outbuf is
    generic(
        IN_WIDTH        : integer := 24;
        OUT_WIDTH       : integer := 8;
        BYTE_ORDER      : integer := 1;
        ERR_MODE        : integer := 1
    );
    port(
        pop_clk         : in     vl_logic;
        pop_rst_n       : in     vl_logic;
        pop_req_n       : in     vl_logic;
        fifo_empty      : in     vl_logic;
        data_in         : in     vl_logic_vector;
        data_out        : out    vl_logic_vector;
        pop_wd_n        : out    vl_logic;
        part_wd         : out    vl_logic;
        pop_error       : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IN_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of OUT_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of BYTE_ORDER : constant is 1;
    attribute mti_svvh_generic_type of ERR_MODE : constant is 1;
end dti_asym_outbuf;
